1. Field of the Invention
This invention relates to input circuits, for example, to input circuits of dynamic RAMs (Random Access Memories).
2. Description of the Prior Art
Conventionally, for example, in dynamic RAMs, internal circuits such as sense amplifiers (e.g., 2.sup.10 =1024 sense amplifier circuits in the case of a 1 mega-bit DRAM or the like operate in reading data as output from memories, writing data for input to memories, or the like. At this time a large amount of current momentarily flows at a ground side (ground lines) of the internal circuits. Therefore, an electric potential (V.sub.SS) at the ground side momentarily rises, and noise is momentarily generated, which may induce the circuits to malfunction.
Malfunction of the circuits caused by the generation of noise in the above dynamic RAMs or the like is likely to occur, for example, in input circuits of CMOS (Complementary MOS) circuits or the like between row address inputs and row address buffers.
With regard to FIG. 9, an A.multidot.I (address input) terminal is respectively connected to a gate of an N channel MOS transistor N.sub.1 and to a gate of a P channel MOS transistor P.sub.1, and the P channel MOS transistors P.sub.1 and P.sub.2 are respectively connected in parallel (i.e., sources of P.sub.1 and P.sub.2 are connected, and drains of P.sub.1 and P.sub.2 are connected, respectively), and the sources of MOS transistors P.sub.1 and P.sub.2 are respectively connected to a power supply side (V.sub.DD). Furthermore, a gate of the P channel MOS transistor P.sub.2 is connected to a gate of an N channel MOS transistor N.sub.2 and to a clock YAN (e.g., 4.5V: a clock which makes the above address buffer circuit active). The drains of P channel MOS transistors P.sub.1 and P.sub.2 are respectively connected to a drain of the N channel MOS transistor N.sub.1 ; a source of the transistor N.sub.1 is connected to a drain of the transistor N.sub.2 ; and a source of the transistor N.sub.2 is connected to the ground side (V.sub.SS), all of which constitutes an input circuit stage 1a.
Also, the drain of the N channel MOS transistor N.sub.1 (or the drains of the P channel MOS transistors P.sub.1 and P.sub.2) is respectively connected to a gate of a P channel MOS transistor P.sub.3 and to a gate of an N channel MOS transistor N.sub.3. A source of the transistor P.sub.3 is connected to the power supply side (V.sub.DD), and its drain is connected to a drain of the transistor N.sub.3. Moreover, a source of the transistor N.sub.3 is connected to the ground side (V.sub.SS), and the drains of the P channel transistor P.sub.3 and the N channel transistor N.sub.3 are respectively connected to an output terminal Y.sub.2, all of which constitutes an inverter stage 1b.
The above input circuit stage 1a and inverter stage 1b of FIG. 9 constitute an input circuit 1.
Next, referring to the operation of the input circuit 1 with regard to FIGS. 9 and 3, when the A.multidot.I (input) terminal is at the level "L", the P channel MOS transistor P.sub.1 turns on; the N channel MOS transistor N.sub.2 turns off; and an electric potential at the point E turns to the level "H". Furthermore, the P channel MOS transistor P.sub.3 turns off; the N channel MOS transistor N.sub.3 turns on; and the level "L" is output at the terminal Y.sub.2 (output).
Next, when the A.multidot.I (input) terminal is at the level "H", the P channel MOS transistor P.sub.1 turns off; the N channel MOS transistor N.sub.1 turns on; and an electric potential at the point E turns to the level "L". The P channel MOS transistor P.sub.3 turns on; the N channel MOS transistor N.sub.3 turns off; and the level "H" is output at the terminal Y.sub.2 (output).
Because a voltage, for example 4.5V, is always applied by the clock YAN to the gates of the P channel MOS transistor P.sub.2, N.sub.2, and the N channel MOS transistor N.sub.2, the transistor P.sub.2 is always in the off state, and the transistor N.sub.2 is always in the on state. The inverter stage 1b operates normally without any effect from noise.
The description which follows illustrates a case in which noise occurred at the ground side (V.sub.SS), because of a reason such as the above, at one moment of the time when the A.multidot.I terminal (input) is at the level "H". In the input signal level of dynamic RAMs in general, for example, the level "H" is 2.4V and above; the level "L" is 0.8V and below; and a threshold voltage is generally set at about 1.6V. If an electric potential rise (noise), for example of 2V, occurs momentarily at the ground side (V.sub.SS), a threshold voltage (e.g., about 1.6V) of the input circuit stage 1a (outer input level) will be immediately surpassed.
Therefore, as described above, the electric potential at the point E, which should be at the level "L", turns to the level "H" at the moment the noise occurs, and the level "L" is momentarily output at the Y.sub.2 terminal which should have the level "H" output, as shown by the curve e in the time chart of FIG. 3 (i.e., this will be a cause for a malfunction of the internal circuit). This will adversely affect, for example, a row address buffer which will be later described.
Therefore, to reduce the noise at the ground side (V.sub.SS), the ground lines could be made larger, or a ground line could be connected to the row address buffer, but these approaches will have an unfavorable effect in efforts to minimize the elements of an electronic device, such as a DRAM.
Also, in CMOS circuits as in NMOS circuits, a method (a so-called sensing method) could be utilized in which a noise which is similar to the one generated at the ground side is applied to an input circuit side and a reference side. However, this sensing method requires a reference voltage generation circuit or the like, which makes the circuits complicated and delays the operation speed of the circuits, so that this method is not generally used in the CMOS circuits or the like.
As shown in FIGS. 10 (a), (b), and (c), in a CMOS circuit (an inverter in this case), a threshold voltage V.sub.th of an input circuit is generally controlled by the relative channel sizes of a P channel MOS transistor P.sub.0 and an N channel MOS transistor N.sub.0. That is, by keeping a channel length L constant, a ratio (W.sub.1 /W.sub.2) of a channel width W.sub.1 of the P channel MOS transistor P.sub.0 and a channel width W.sub.2 of the N channel MOS transistor N.sub.0 determines the threshold voltage V.sub.th, as shown by the curve f in FIG. 10 (c).
Therefore, as in the above, the threshold voltage V.sub.th is determined by the transistor size when the transistor is being designed, and once it is determined, the threshold voltage V.sub.th cannot be controlled by the same method.